Comments on: C2020 Computer Architecture Term 3 2008 Assignment

By: physician assistant

physician assistant — Mon, 12 Jul 2010 14:21:32 +0000

nice post. thanks.

By: Hasitha

Hasitha — Thu, 24 Jun 2010 01:59:01 +0000

Did anyone can answer to “Lois” question. I too have the same problem.
Expecting you a quick reply.

By: Lois

Lois — Wed, 02 Jun 2010 03:31:06 +0000

. Instruction, sub[A],[B],[C], subtracts number stored in address A to address B and then
stores the result into address C. Assume instruction is stored at address 4D, show the
fetch and execute steps. [20 marks]

2. Write the assembly codes for expression M = A-B/(C+D)*F-E using Zero, One,
Two and three address-format machines [25 marks]

3. A 3 address-format machine is able to access 10000 different memory locations,
150 different general purpose registers and issue 400 different commands. Allocate the
appropriate number of bits to the different parts of the IR. State the total length of IR
and the number of direct addressable locations. [5 marks]

4. The processor speed has increase tremendously for the last 10 years. Discuss about the
speed of different processors and explain why there is a need for the increment of
processor speed at this rate.

Pls help me and answer this question.

Thanks
Lois

By: Steve

Steve — Sat, 29 May 2010 01:46:12 +0000

hi;

where did you get the formula to calculate the number of operand bits?
i have a similar question to answer, but they i do not have the data bus size, instead i have the MAR size which is 14 bits?

please help.

regadrs

By: Bruce

Bruce — Fri, 21 May 2010 07:16:07 +0000

hi;

where did you get the formula to calculate the number of operand bits?
i have a similar question to answer, but they i do not have the data bus size, instead i have the MAR size which is 14 bits?

please help.

regadrs

By: Michelle

Michelle — Tue, 20 Apr 2010 16:26:35 +0000

@cedrix
Hi;

Sorry for the delay. Actually for question 1, the size of opearnd field is going to be the size of MAR that is 14 bits.

The other question is addressed in the course slides. There is no frmula for it though. You need to under stand what LRU is and what FIFO is.

FIFO is: First-in, First-out (FIFO): Evict the page that has been in the cache the longest

LRU is: Least recently used (LRU): Evict the page whose last request occurred furthest in the past.

i hope it helps.

regards\

By: jay

jay — Sun, 06 Dec 2009 15:25:43 +0000

@cedrix
Hi;

Sorry for the delay. Actually for question 1, the size of opearnd field is going to be the size of MAR that is 14 bits.

The other question is addressed in the course slides. There is no frmula for it though. You need to under stand what LRU is and what FIFO is.

FIFO is: First-in, First-out (FIFO): Evict the page that has been in the cache the longest

LRU is: Least recently used (LRU): Evict the page whose last request occurred furthest in the past.

i hope it helps.

regards\

By: cedrix

cedrix — Tue, 24 Nov 2009 08:11:15 +0000

Jay, I am doing the same assignment, 3address-format machine, 14bits MAR, able to access 2000 different commands and access 250 different GPR. I’ve been searching for the formula.

another question need formula-
The stream of address 1,2,1,3,4,5,3,6,7,2,1,7,8,3 is to be entered, serially, into the cache that can only hold 3 addresses at a time. Using FIFO and LRU replacement policies; show the status of the cache, indicate hits if any, as the addresses are entered into it. [10 marks]

By: jay

jay — Wed, 18 Nov 2009 10:10:39 +0000

hi;

where did you get the formula to calculate the number of operand bits?
i have a similar question to answer, but they i do not have the data bus size, instead i have the MAR size which is 14 bits?

please help.

regadrs

By: Start Posting the second series of IADIC Assignments | Thomaset2000's Room

Start Posting the second series of IADIC Assignments | Thomaset2000's Room — Fri, 27 Feb 2009 12:41:26 +0000

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