C2020 Computer Architecture Term 3 2008 Assignment
Hi All!
To begin the second series of IADIC assignments posting series, I will post the assignment of C2020 Computer Architecture module that I take in Term 3 2008.
This module teach about how the computer’s processor works technically and also things like pipelining, virtual memory, assembly language, memory organization, LAN, TCP IP, etc.
The assignment is quite short and maybe the shortest assingment for IADIC (International Advanced Diploma in Computing) module. It consist of three questions
here is the assignment questions:
The total mark of the assignment is 40 divided by these three questions:
Question 1.
A three address-format machine has 128 data bus channels and is able to accept 1000 different commands and access 120 different general purpose registers. Show clearly, in workings, the allocation of bits to the different fields of the Instruction registers. Give the total length of IR and the number of direct addressable locations. [7 marks]
Question 2.
Instruction Add [101] [102][103] adds number stored in address 101 to number in address 102 and then stores the results into address 103. Show clearly the fetch and execution steps.
Note: You may make assumption on the address that stores the instruction. [13 marks]
Question 3.
Given expression Y = M-N*A+B/R*C, provide the assembly codes for Zero, One, Two and Three address-format machines. [20 marks]
and here is my answer for these questions
Answer
II. Answer for Question 1
- Three address format machine
- Data bus width = 128 bits
- Total accessible General Purpose Registers (GPR) = 120
- Total acceptable commands = 1000
No. of bits in GPR field = 7 → 27 = 128 > accessible General Purpose Registers
No. of bits in Opcode field = 10 → 210 = 1024 > acceptable commands
No. of bits in Operand field = (DatabusWidth – opcode – GPR)/no.of Operand Field = (128 – 10 – 7)/3 = 37
Instruction Register Fields:
| Opcode | Operand | Operand | Operand | GPR |
| 10 | 37 | 37 | 37 | 7 |
The total length of IR = 10 + 37 + 37 + 37 + 7 = 128
Number of direct addressable locations = 2operand = 237 = 137438953472
III. Answer for Question 2
Fetch cycle:
| 1. | 0110 | → | PC | → | MAR | → | Address bus | |||||||||
| 2. | Read control line asserted | |||||||||||||||
| 3. | [Add[101] [102] [103]]0110 | → | Data bus | → | MBR | → | IR | |||||||||
| 4. | PC = PC + 1 | |||||||||||||||
Execution cycle:
| 1. | IR | → | Decoding | |||||||||||||||||
| 2. | [101] | → | MAR | → | Address bus | |||||||||||||||
| 3. | Read control line asserted | |||||||||||||||||||
| 4. | [data]101 | → | Data bus | → | MBR | → | Ax | |||||||||||||
| 5. | [102] | → | MAR | → | Address bus | |||||||||||||||
| 6. | Read control line asserted | |||||||||||||||||||
| 7. | [data]102 | → | Data bus | → | MBR | → | Ax | |||||||||||||
| 8. | [103] | → | MAR | → | Address bus | |||||||||||||||
| 9. | Write control line asserted | |||||||||||||||||||
| 10. | Ax | → | MBR | → | Data bus | → | [result]103 | |||||||||||||
IV. Answer for Question 3
Expression → Y = M-N*A+B/R*C
| Zero Address | One Address | Two Address | Three Address |
| PUSH M | LOAD N | MUL N, A | MUL N, A, T1 |
| PUSH N | MUL A | DIV B, R | DIV B, R, T2 |
| PUSH A | STO T1 | MUL R, C | MUL T2, C, T3 |
| MUL | LOAD B | SUB M, A | SUB M, T1, T4 |
| SUB | DIV R | ADD A, C | ADD T4, T3, Y |
| PUSH B | MUL C | MOV C, Y | |
| PUSH R | STO T2 | ||
| DIV | LOAD M | ||
| PUSH C | SUB T1 | ||
| MUL | ADD T2 | ||
| ADD | STO Y | ||
| POP Y |
Do you have any comment on this? maybe you have something to ask me or want to discuss with me about this?Or maybe you are IDIC student and taking this module also?
Feel free to use the comment box below (click here if you cannot see the comment box).
Coming next, I will post another IADIC assignment, C2027 Information Management 
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hi;
where did you get the formula to calculate the number of operand bits?
i have a similar question to answer, but they i do not have the data bus size, instead i have the MAR size which is 14 bits?
please help.
regadrs
Jay, I am doing the same assignment, 3address-format machine, 14bits MAR, able to access 2000 different commands and access 250 different GPR. I’ve been searching for the formula.
another question need formula-
The stream of address 1,2,1,3,4,5,3,6,7,2,1,7,8,3 is to be entered, serially, into the cache that can only hold 3 addresses at a time. Using FIFO and LRU replacement policies; show the status of the cache, indicate hits if any, as the addresses are entered into it. [10 marks]
@cedrix
Hi;
Sorry for the delay. Actually for question 1, the size of opearnd field is going to be the size of MAR that is 14 bits.
The other question is addressed in the course slides. There is no frmula for it though. You need to under stand what LRU is and what FIFO is.
FIFO is: First-in, First-out (FIFO): Evict the page that has been in the cache the longest
LRU is: Least recently used (LRU): Evict the page whose last request occurred furthest in the past.
i hope it helps.
regards\
@cedrix
Hi;
Sorry for the delay. Actually for question 1, the size of opearnd field is going to be the size of MAR that is 14 bits.
The other question is addressed in the course slides. There is no frmula for it though. You need to under stand what LRU is and what FIFO is.
FIFO is: First-in, First-out (FIFO): Evict the page that has been in the cache the longest
LRU is: Least recently used (LRU): Evict the page whose last request occurred furthest in the past.
i hope it helps.
regards\
hi;
where did you get the formula to calculate the number of operand bits?
i have a similar question to answer, but they i do not have the data bus size, instead i have the MAR size which is 14 bits?
please help.
regadrs
hi;
where did you get the formula to calculate the number of operand bits?
i have a similar question to answer, but they i do not have the data bus size, instead i have the MAR size which is 14 bits?
please help.
regadrs
. Instruction, sub[A],[B],[C], subtracts number stored in address A to address B and then
stores the result into address C. Assume instruction is stored at address 4D, show the
fetch and execute steps. [20 marks]
2. Write the assembly codes for expression M = A-B/(C+D)*F-E using Zero, One,
Two and three address-format machines [25 marks]
3. A 3 address-format machine is able to access 10000 different memory locations,
150 different general purpose registers and issue 400 different commands. Allocate the
appropriate number of bits to the different parts of the IR. State the total length of IR
and the number of direct addressable locations. [5 marks]
4. The processor speed has increase tremendously for the last 10 years. Discuss about the
speed of different processors and explain why there is a need for the increment of
processor speed at this rate.
Pls help me and answer this question.
Thanks
Lois
Did anyone can answer to “Lois” question. I too have the same problem.
Expecting you a quick reply.